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RISC-V targets data centers, edge AI, space EE Times 6d

EE Times 6d

Space Exploration

RISC-V Summit Europe 2026: Industry and academia unite in Bologna to advance open hardware EE Times 17:18 Mon, 08 Jun

EE Times 17:18 Mon, 08 Jun

2 to 4 cents Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor Engine (ME2) core CNX Software 6d

CNX Software 6d

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Openchip taps Baya Systems data-movement platform for RISC-V systems SiliconANGLE 7d

SiliconANGLE 7d

OpenCV 5 release – New Dnn engine with enhanced Onnx and Llm/Vlm support, Intel, Arm, and RISC-V hardware optimizations CNX Software 8d

CNX Software 8d

Intel Processors

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Michael Chapman, CEO of Cortus, on RISC-V, AI, and Europe’s semiconductor future eeNews Analog 7d

eeNews Analog 7d

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Latest

Yesterday

Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board CNX Software 12:48 Wed, 17 Jun

Tuesday

RISC-V Silicon in the Jungle Could Save the Amazon EE Times 09:49 Tue, 16 Jun

Monday

Linux 7.1 Release – Main changes, Arm, RISC-V, and MIPS architectures CNX Software 12:29 Mon, 15 Jun

Friday

2 to 4 cents Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor Engine (ME2) core CNX Software 09:09 Fri, 12 Jun

In the last month

RISC-V Targets Data Centers, Edge AI, Space EE Times 14:29 Thu, 11 Jun

Openchip taps Baya Systems data-movement platform for RISC-V systems SiliconANGLE 11:01 Thu, 11 Jun

Michael Chapman, CEO of Cortus, on RISC-V, AI, and Europe’s semiconductor future eeNews Analog 20:19 Wed, 10 Jun

NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC Business Wire (Press Release) 10:01 Wed, 10 Jun

OpenCV 5 release – New DNN engine with enhanced ONNX and LLM/VLM support, Intel, Arm, and RISC-V hardware optimizations CNX Software 05:16 Wed, 10 Jun

RISC-V Summit Europe 2026: Industry and Academia Unite in Bologna to Advance Open Hardware EE Times 17:18 Mon, 08 Jun

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